The present invention relates to a semiconductor memory, and more specifically to a semiconductor memory so configured to receive and output data in synchronism with an input clock.
Recently, with a high processing speed in an image processor, a memory capable of reading and writing an image data at a high speed has become demanded. As one means for meeting with this demand, a high speed DRAM (dynamic random access memory) called a "synchronous DRAM" or a "synchronous graphic DRAM" is coming into a wide use.
For example, the synchronous DRAM includes two banks having independent address spaces, respectively, so that each bank can operate independently of the other. In addition, the synchronous DRAM realizes a high speed access of data by a burst operation in which data in continuous addresses in the same row space is sequentially accessed.
However, in controlling the conventional synchronous memory such as the synchronous DRAM, a reading or writing operation is executed in response to a plurality of commends in combination from a CPU (central processing unit) or another. Therefore, some operation is repeatedly executed, it is necessary to repeatedly supply a corresponding train of commands. Accordingly, in order to increase the efficiency of data processing by the burst operation, namely, by a processing typified by a bank interleaving, it is necessary to request a complicated processing to a memory controller. Here, a control command is an operation instruction to the memory, and instructs, for example, an activation of a word line corresponding to a given row address, a precharging of bit lines, for an accessing to an memory cell designated by an address signal, in some bank.
Furthermore, a recent tendency of the synchronous DRAM is that the operation frequency has already exceeded 100 MHz and is going to further reach 125 MHz or 143 MHz, with the result that the control command train becomes further complicated. This has become a large load on the memory controller.